CVE-2026-98919
CVE-2026-98919 · drm/xe: harden adjust_idledly() against divide-by-zero and overflow
This page contains facts from public vulnerability sources. Check the original advisory before updating.
In the Linux kernel, the following vulnerability has been resolved: drm/xe: harden adjust_idledly() against divide-by-zero and overflow adjust_idledly() has several corner-case issues flagged during review: 1. If xe_gt_clock_init() failed to recognise the crystal clock, gt->info.timestamp_base is 0, which makes idledly_units_ps also 0. The subsequent DIV_ROUND_CLOSEST(..., idledly_units_ps) is then a divide-by-zero and panics the kernel. 2. The tick-to-ns conversions are done in u32: idledly * idledly_units_ps, (maxcnt - 1) * 1000 Both overflow u32 before DIV_ROUND_CLOSEST() sees them. 3. If IDLE_WAIT_TIME reads back as 0, maxcnt evaluates to 0 and the maxcnt - 1 clamp wraps to 0xFFFFFFFF in u32. 4. The register only stores whole ticks, so the clamped ns value has to be converted to ticks and back. DIV_ROUND_CLOSEST() can round that conversion up past maxcnt: maxcnt = 640 ns, one tick = 666664 ps clamp: maxcnt - 1 = 639 ns ns -> ticks: 639000 / 666664 = 0.958 -> rounds to 1 tick tick -> ns: 1 * 666664 / 1000 = 667 ns 667 ns is programmed into RING_IDLEDLY, but 667 >= maxcnt (640), so xe_gt_WARN_ON() fires again on every subsequent init. Return early if timestamp_base is 0 (the unknown-crystal path). Do the conversions in u64 via the *_ULL() helpers so they cannot wrap. Clamp with a floor (DIV_ROUND_DOWN_ULL) so the programmed delay stays strictly below maxcnt, and guard the maxcnt == 0 case with a zero delay while still writing RING_IDLEDLY so INHIBIT_SWITCH_UNTIL_PREEMPTED is cleared. v2: Drop the redundant warn on the timestamp_base == 0 path; xe_gt_clock_init() already warns on an unrecognised crystal clock. Keep the early return to avoid the divide-by-zero. - Vinay v3: Field-mask the RING_IDLEDLY write with REG_FIELD_PREP(IDLE_DELAY, ...) instead of writing the raw tick count, which could clobber INHIBIT_SWITCH_UNTIL_PREEMPTED and reserved bits. Split the inhibit-switch clear from the maxcnt clamp so a set inhibit bit no longer forces a needless delay overwrite when the delay itself is already valid. Use gt_to_xe(gt) instead of gt_to_xe(hwe->gt). (cherry picked from commit d864065ea25e9d12897c175de9176ce46677e176)
EPSS 0.2% · Fix available
- Published
- Updated
Stack: system
Affected products and versions
linux
- Versions
- ≥ d2de4410a88ffc6053300d03041cc73b8c85dbaf, < 2bcbfc5e7bfa9cc76818c54db698da5bdc13d9ff: Affected (git)
- ≥ d2de4410a88ffc6053300d03041cc73b8c85dbaf, < 531d4cd03118224022dc21ae25af052ce2a9e267: Affected (git)
- ≥ d2de4410a88ffc6053300d03041cc73b8c85dbaf, < 90f467577ebc28c5bc4ba2f0f1b83a4419fb0740: Affected (git)
Update to 2bcbfc5e7bfa9cc76818c54db698da5bdc13d9ff
linux
- Versions
- 6.15: Affected
- ≥ 0, < 6.15: Not affected (semver)
- ≥ 6.18.55, ≤ 6.18.*: Not affected (semver)
- ≥ 7.2.9, ≤ 7.2.*: Not affected (semver)
- ≥ 7.3: Not affected (original_commit_for_fix)
No fix published
linux Debian:14
- Versions
- 6.12.100-1
- 6.12.101-1
- 6.12.105-1
- 6.12.107-1
- 6.12.111-1
- 6.12.113-1
- 6.12.38-1
- 6.12.41-1
- 6.12.43-1
- 6.12.43-1~bpo12+1
- 6.12.48-1
- 6.12.57-1
- 6.12.57-1~bpo12+1
- 6.12.63-1
- 6.12.63-1~bpo12+1
- 6.12.69-1
- 6.12.69-1~bpo12+1
- 6.12.73-1
- 6.12.73-1~bpo12+1
- 6.12.74-1
- 6.12.74-2
- 6.12.74-2~bpo12+1
- 6.12.85-1
- 6.12.85-1~bpo12+1
- 6.12.86-1
- 6.12.86-1~bpo12+1
- 6.12.88-1
- 6.12.88-1~bpo12+1
- 6.12.90-1
- 6.12.90-1~bpo12+1
- 6.12.90-2
- 6.12.90-2~bpo12+1
- 6.12.94-1
- 6.12.94-1~bpo12+1
- 6.12.95-1
- 6.12.95-1~bpo12+1
- 6.12.96-1
- 6.13.10-1~exp1
- 6.13.11-1~exp1
- 6.13.2-1~exp1
- 6.13.3-1~exp1
- 6.13.4-1~exp1
- 6.13.5-1~exp1
- 6.13.6-1~exp1
- 6.13.7-1~exp1
- 6.13.8-1~exp1
- 6.13.9-1~exp1
- 6.13~rc6-1~exp1
- 6.13~rc7-1~exp1
- 6.14.3-1~exp1
- 6.14.5-1~exp1
- 6.14.6-1~exp1
- 6.15-1~exp1
- 6.15.1-1~exp1
- 6.15.2-1~exp1
- 6.15.3-1~exp1
- 6.15.4-1~exp1
- 6.15.5-1~exp1
- 6.15.6-1~exp1
- 6.15~rc7-1~exp1
- 6.16-1~exp1
- 6.16.1-1~exp1
- 6.16.10-1
- 6.16.11-1
- 6.16.12-1
- 6.16.12-1~bpo13+1
- 6.16.12-2
- 6.16.3-1
- 6.16.3-1~bpo13+1
- 6.16.5-1
- 6.16.6-1
- 6.16.7-1
- 6.16.8-1
- 6.16.9-1
- 6.16~rc7-1~exp1
- 6.17.10-1
- 6.17.11-1
- 6.17.12-1
- 6.17.13-1
- 6.17.13-1~bpo13+1
- 6.17.2-1~exp1
- 6.17.5-1~exp1
- 6.17.6-1
- 6.17.7-1
- 6.17.7-2
- 6.17.8-1
- 6.17.8-1~bpo13+1
- 6.17.9-1
- 6.18.1-1~exp1
- 6.18.10-1
- 6.18.12-1
- 6.18.12-1~bpo13+1
- 6.18.13-1
- 6.18.14-1
- 6.18.15-1
- 6.18.15-1~bpo13+1
- 6.18.2-1~exp1
- 6.18.3-1
- 6.18.5-1
- 6.18.5-1~bpo13+1
- 6.18.8-1
- 6.18.9-1
- 6.18.9-1~bpo13+1
- 6.18~rc4-1~exp1
- 6.18~rc4-1~exp2
- 6.18~rc5-1~exp1
- 6.18~rc6-1~exp1
- 6.18~rc7-1~exp1
- 6.19-1~exp1
- 6.19.10-1
- 6.19.10-1~bpo13+1
- 6.19.11-1
- 6.19.11-1~bpo13+1
- 6.19.12-1
- 6.19.13-1
- 6.19.13-1~bpo13+1
- 6.19.14-1
- 6.19.14-1~bpo13+1
- 6.19.2-1~exp1
- 6.19.3-1~exp1
- 6.19.4-1~exp1
- 6.19.5-1~exp1
- 6.19.6-1
- 6.19.6-2
- 6.19.6-2~bpo13+1
- 6.19.8-1
- 6.19.8-1~bpo13+1
- 6.19~rc4-1~exp1
- 6.19~rc5-1~exp1
- 6.19~rc6-1~exp1
- 6.19~rc7-1~exp1
- 6.19~rc8-1~exp1
- 7.0-1~exp1
- 7.0.1-1~exp1
- 7.0.10-1
- 7.0.10-1~bpo13+1
- 7.0.12-1
- 7.0.12-2
- 7.0.12-2~bpo13+1
- 7.0.13-1
- 7.0.13-1~bpo13+1
- 7.0.14-1
- 7.0.3-1
- 7.0.4-1
- 7.0.4-1~bpo13+1
- 7.0.7-1
- 7.0.7-1~bpo13+1
- 7.0.9-1
- 7.0.9-1~bpo13+1
- 7.1.1-1~exp1
- 7.1.10-1
- 7.1.12-1
- 7.1.13-1
- 7.1.13-1~bpo13+1
- 7.1.2-1~exp1
- 7.1.3-1
- 7.1.3-1+sunvdc
- 7.1.3-1~bpo13+1
- 7.1.4-1
- 7.1.5-1
- 7.1.6-1
- 7.1.7-1
- 7.1.7-1~bpo13+1
- 7.1.8-1
- 7.1.8-1~bpo13+1
- 7.1.8-2
- 7.1.9-1
- 7.1.9-1+sparc64
- 7.1~rc2-1~exp1
- 7.1~rc3-1~exp1
- 7.1~rc4-1~exp1
- 7.1~rc4-1~exp2
- 7.1~rc5-1~exp1
- 7.1~rc7-1~exp1
- 7.2.2-1~exp1
- 7.2.3-1~exp1
- 7.2.6-1
- 7.2.6-1~bpo13+1
- 7.2.7-1
- 7.2.8-1
- 7.2.9-1~bpo13+1
- 7.2~rc3-1~exp1
- 7.2~rc5-1~exp1
- 7.2~rc7-1~exp1
- Affected ranges
- ECOSYSTEM: < 7.2.9-1
Update to 7.2.9-1